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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M68ICS08GR 데이터시트(PDF) 331 Page - Freescale Semiconductor, Inc |
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M68ICS08GR 데이터시트(HTML) 331 Page - Freescale Semiconductor, Inc |
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331 / 408 page  Timebase Module (TBM) Timebase Register Description MC68HC908GR8 — Rev 4.0 Technical Data MOTOROLA Timebase Module (TBM) 331 21.5 Timebase Register Description The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate. TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over. 1 = Timebase interrupt pending 0 = Timebase interrupt not pending TBR2:TBR0 — Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Table 21-1. Address: $001C Bit 7 654321 Bit 0 Read: TBIF TBR2 TBR1 TBR0 0 TBIE TBON Reserved Write: TACK Reset: 00000000 = Unimplemented Figure 21-2. Timebase Control Register (TBCR) Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz TBR2 TBR1 TBR0 Divider Timebase Interrupt Rate Hz ms 0 0 0 32,768 1 1000 0 0 1 8192 4 250 0 1 0 2048 16 62.5 0 1 1 128 256 ~ 3.9 1 0 0 64 512 ~2 1 0 1 32 1024 ~1 1 1 0 16 2048 ~0.5 1 1 1 8 4096 ~0.24 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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