M68ICS08GR datasheet(72/408 Pages) FREESCALE

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Resets and Interrupts

Technical Data

MC68HC908GR8 — Rev 4.0

Resets and Interrupts

MOTOROLA

4.4.2.6 TIM2

TIM2 CPU interrupt sources:

•

TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2

counter value rolls over to $0000 after matching the value in the

TIM2 counter modulo registers. The TIM2 overflow interrupt

enable bit, TOIE, enables TIM2 overflow CPU interrupt requests.

TOF and TOIE are in the TIM2 status and control register.

•

TIM2 channel flag (CH0F) — The CH0F bit is set when an input

capture or output compare occurs on channel 0. The channel 0

interrupt enable bit, CH0IE, enables channel 0 TIM2 CPU interrupt

requests. CH0F and CH0IE are in the TIM2 channel 0 status and

control register.

4.4.2.7 SPI

SPI CPU interrupt sources:

•

SPI receiver full bit (SPRF) — The SPRF bit is set every time a

byte transfers from the shift register to the receive data register.

The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU

interrupt requests. SPRF is in the SPI status and control register

and SPRIE is in the SPI control register.

•

SPI transmitter empty (SPTE) — The SPTE bit is set every time a

byte transfers from the transmit data register to the shift register.

The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU

interrupt requests. SPTE is in the SPI status and control register

and SPTIE is in the SPI control register.

•

Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the

SS pin goes high during a transmission with the mode fault enable

bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS

pin goes low at any time with the MODFEN bit set. The error

interrupt enable bit, ERRIE, enables MODF CPU interrupt

requests. MODF, MODFEN, and ERRIE are in the SPI status and

control register.

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