M68ICS08GR datasheet(51/408 Pages) FREESCALE

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Low Power Modes

Break Module (BRK)

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Low Power Modes

3.4 Break Module (BRK)

3.4.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine,

the user can subtract one from the return address on the stack if the BW

bit in the break status register is set.

3.4.2 Stop Mode

The break module is inactive in stop mode. A break interrupt causes exit

from stop mode and sets the BW bit in the break status register. The

STOP instruction does not affect break module register states.

3.5 Central Processor Unit (CPU)

3.5.1 Wait Mode

The WAIT instruction:

•

Clears the interrupt mask (I bit) in the condition code register,

enabling interrupts. After exit from wait mode by interrupt, the I bit

remains clear. After exit by reset, the I bit is set.

•

Disables the CPU clock

3.5.2 Stop Mode

The STOP instruction:

•

Clears the interrupt mask (I bit) in the condition code register,

enabling external interrupts. After exit from stop mode by external

interrupt, the I bit remains clear. After exit by reset, the I bit is set.

•

Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator

stabilization delay.

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M68ICS08GR 데이터시트(PDF) 51 Page - Freescale Semiconductor, Inc