M68ICS08GR datasheet(50/408 Pages) FREESCALE

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Low Power Modes

Technical Data

MC68HC908GR8 — Rev 4.0

Low Power Modes

MOTOROLA

3.2.1 Wait Mode

The WAIT instruction puts the MCU in a low-power standby mode in

which the CPU clock is disabled but the bus clock continues to run.

Power consumption can be further reduced by disabling the LVI module

and/or the timebase module through bits in the CONFIG register. (See

Configuration Register (CONFIG).)

3.2.2 Stop Mode

Stop mode is entered when a STOP instruction is executed. The CPU

clock is disabled and the bus clock is disabled if the OSCSTOPENB bit

in the CONFIG register is at a logic 0. (See Configuration Register

(CONFIG).)

3.3 Analog-to-Digital Converter (ADC)

3.3.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled

CPU interrupt request from the ADC can bring the MCU out of wait

mode. If the ADC is not required to bring the MCU out of wait mode,

power down the ADC by setting ADCH4–ADCH0 bits in the ADC status

and control register before executing the WAIT instruction.

3.3.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction.

Any pending conversion is aborted. ADC conversions resume when the

MCU exits stop mode after an external interrupt. Allow one conversion

cycle to stabilize the analog circuitry.

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