M68ICS08GR datasheet(143/408 Pages) FREESCALE

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Central Processing Unit (CPU)

CPU registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Central Processing Unit (CPU)

143

During reset, the program counter is loaded with the reset vector

address located at $FFFE and $FFFF. The vector address is the

address of the first instruction to be executed after exiting the reset state.

10.4.5 Condition code register (CCR)

The 8-bit condition code register contains the interrupt mask and five

flags that indicate the results of the instruction just executed. Bits 6 and

5 are set permanently to ‘1’. The following paragraphs describe the

functions of the condition code register.

V — Overflow flag

The CPU sets the overflow flag when a two's complement overflow

occurs. The signed branch instructions BGT, BGE, BLE, and BLT use

the overflow flag.

1 = Overflow

0 = No overflow

H — Half-carry flag

Bit

8765

4321

Bit

Read:

Write:

Reset:

Loaded with vector from $FFFE and $FFFF

Figure 10-5. Program counter (PC)

Bit 7

654321

Bit 0

CCR

Read:

Write:

Reset:

1X1X

X = Indeterminate

Figure 10-6. Condition code register (CCR)

Freescale Semiconductor, Inc.

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