M68ICS08GR datasheet(172/408 Pages) FREESCALE

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External Interrupt (IRQ)

Technical Data

MC68HC908GR8 — Rev 4.0

172

External Interrupt (IRQ)

MOTOROLA

12.7 IRQ Status and Control Register

The IRQ status and control register (INTSCR) controls and monitors

operation of the IRQ module. The INTSCR:

•

Shows the state of the IRQ flag

•

Clears the IRQ latch

•

Masks IRQ interrupt request

•

Controls triggering sensitivity of the IRQ1 interrupt pin

IRQF — IRQ Flag Bit

This read-only status bit is high when the IRQ interrupt is pending.

1 = IRQ interrupt pending

0 = IRQ interrupt not pending

ACK — IRQ Interrupt Request Acknowledge Bit

Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always

reads as logic 0. Reset clears ACK.

IMASK — IRQ Interrupt Mask Bit

Writing a logic 1 to this read/write bit disables IRQ interrupt requests.

Reset clears IMASK.

1 = IRQ interrupt requests disabled

0 = IRQ interrupt requests enabled

Address:

$001D

Bit 7

654321

Bit 0

Read:

IRQF

IMASK

MODE

Write:

ACK

Reset:

00000000

= Unimplemented

Figure 12-3. IRQ Status and Control Register (INTSCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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