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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VMV3 데이터시트(PDF) 122 Page - Microsemi Corporation |
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VMV3 데이터시트(HTML) 122 Page - Microsemi Corporation |
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122 / 212 page  Military ProASIC3/EL DC and Switching Characteristics 2-108 Revision 3 Table 2-182 • Input DDR Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for any A3PE600L/A3PE3000L Parameter Description –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.29 0.34 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.41 0.48 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.30 0.35 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.26 0.31 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.49 0.58 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.60 0.71 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.24 0.28 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 0.22 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 0.36 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 0.32 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-183 • Input DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.33 0.39 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.47 0.55 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.30 0.35 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.30 0.35 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.56 0.65 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.69 0.81 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.27 0.31 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.25 0.30 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.41 0.48 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.37 0.43 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. |
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