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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VMV3 데이터시트(PDF) 124 Page - Microsemi Corporation |
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VMV3 데이터시트(HTML) 124 Page - Microsemi Corporation |
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124 / 212 page  Military ProASIC3/EL DC and Switching Characteristics 2-110 Revision 3 Timing Characteristics Figure 2-37 • Output DDR Timing Diagram 11 6 1 7 2 8 3 910 45 28 3 9 tDDROREMCLR tDDROHD1 tDDROREMCLR tDDROHD2 tDDROSUD2 tDDROCLKQ tDDRORECCLR CLK Data_R Data_F CLR Out tDDROCLR2Q 710 4 Table 2-185 • Output DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.97 1.14 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.52 0.62 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.52 0.62 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.11 1.30 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.31 0.36 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 0.22 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 0.36 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 0.32 ns FDDOMAX Maximum Frequency for the Output DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. |
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