VMV3 datasheet(149/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-135

Table 2-206 • RAM512X18

Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L

Parameter

Description

–1

Std. Units

tAS

Address setup time

0.26 0.31

tAH

Address hold time

0.00 0.00

tENS

REN_B, WEN_B setup time

0.10 0.11

tENH

REN_B, WEN_B hold time

0.06 0.07

tDS

Input data (DI) setup time

0.19 0.23

tDH

Input data (DI) hold time

0.00 0.00

tCKQ1

Clock High to new data valid on DO (output retained, WMODE = 0)

2.29 2.69

tCKQ2

Clock High to new data valid on DO (pipelined)

0.95 1.12

tC2CRWH

Address collision clk-to-clk delay for reliable read access after write on same

address – applicable to opening edge

0.18 0.21

tC2CWRH

Address collision clk-to-clk delay for reliable write access after read on same

address – applicable to opening edge

0.21 0.25

tRSTBQ

RESET_B Low to data out Low on DO (flow through)

0.98 1.15

RESET_B Low to data out Low on DO (pipelined)

0.98 1.15

tREMRSTB

RESET_B removal

0.30 0.36

tRECRSTB

RESET_B recovery

1.59 1.87

tMPWRSTB RESET_B minimum pulse width

0.59 0.67

tCYC

Clock cycle time

5.39 6.20

FMAX

Maximum frequency

185 161 MHz

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

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