TNETX15AEPGE datasheet(70/79 Pages) TI1

70 / 79 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Note 7 and Figure 23)

DIO write cycle

NO.

MIN

MAX

UNIT

tw(ESCSL)

Pulse duration, ESCS low

tsu(SRNW)

Setup time, SRNW low before ESCS

↓

tsu(SAD)

Setup time, SAD1–SAD0 valid before ESCS

↓

tsu(SDATA)

Setup time, SDATA7–SDATA0 valid before ESCS

↓

NOTE 7: The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can be

run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register accessed.

The TNETX15AE withholds the SRDY acknowledge signal on registers until it has gathered the necessary data.

operating characteristics over recommended operating conditions (see Note 7 and Figure 23)

DIO write cycle

NO.

PARAMETER

MIN

MAX

UNIT

5†

tw(SRDYH)

Pulse duration, SRDY high

td(SRNW)

Delay time, from SRDY

↓ to SRNW↑

td(SAD)

Delay time, from SRDY

↓ to SAD1–SAD0 invalid

td(SDATA)

Delay time, from SRDY

↓ to SDATA7–SDATA0 high-impedance Z

td(ESCS)

Delay time, from SRDY

↓ to ESCS↑

10†

td(SRDY)1

Delay time, from ESCS

↓ to SRDY↓

‡

11†

td(SRDY)2

Delay time, from ESCS

↑ to SRDY↑

† These parameters are specified by design, but not tested.

‡ Max = min + N (internal cycles), where N equals the number of internal cycles required to arbitrate internally to obtain the value being requested.

N is equal to a minimum of 1, and can be large during RAM INIT and FINDNEXT operation, since DIO operations will not complete during these

operations ( no SRDY true), and both of these operations can read every SRAM location to finish.

NOTE 7: The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can be

run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register accessed.

The TNETX15AE withholds the SRDY acknowledge signal on registers until it has gathered the necessary data.

Data

ESCS

(Input)

SRNW

(Input)

SDATA7–SDATA0

(Input)

SRDY

(Output)

Host Address

SAD1–SAD0

(Input)

Figure 23. DIO Write Cycle

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