TNETX15AEPGE datasheet(73/79 Pages) TI1

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

operating characteristics over recommended operating conditions (see Note 8 and Figure 26)

EEPROM and MDIO (MII) interfaces

When the host is driving the EEPROM interface through the SIO register (0x0A), the output terminals are copies

of register bits synchronized by OSCIN rising, and the input register bits are copies of the device terminals

synchronized by OSCIN rising. This adds a maximum of 20 ns of delay in each direction, which is negligible in

terms of the maximum signal change rate allowed for the EEPROMs (approximately 100 kHz), or the MDIO (MII

management). The timing for these interfaces is set at the rate that register bits are set in software. For detailed

descriptions of the EEPROM requirements, refer to the data sheet for the part in question. For detailed

descriptions of the MII management interface, refer to IEEE Std 802.3.

When the TNETX15VE is driving the EEPROM during the automatic register load cycle, the timing on the

EEPROM is as shown in Figure 26.

EEPROM interface timing (TNETX15AE to EEPROM transfer) (see Note 8)

NO.

PARAMETER†

MIN

MAX

UNIT

fclock

Clock frequency, ECLK

kHz

tw(ECLKL)1

Pulse duration, ECLK low during start/stop

10.24

µs

tw(ECLKH)1

Pulse duration, ECLK high during start/stop

10.2

µs

tw(ECLKH)2

Pulse duration, ECLK high during data

5.1

µs

tw(ECLKL)2

Pulse duration, ECLK low during data

5.12

µs

td(EDIO)1

Delay time, from ECLK

↑ to EDIO↓, start condition

5.1

µs

td(ECLK)1

Delay time, from EDIO

↓ to ECLK↓, start condition

5.1

µs

td(EDIO)2

Delay time, from ECLK

↓ to EDIO↑, data condition

µs

td(ECLK)2

Delay time, from EDIO

↑ to ECLK↑, data condition

5.1

µs

td(EDIO)3

Delay time, from OSCIN to EDIO

td(ECLK)3

Delay time, from OSCIN to ECLK

† These parameters are specified by design, but not tested.

NOTE 8: The timing for the EEPROM interface occurs with the ETEST bit set to 0.

ECLK

(Output)

EDIO

(Output)

Valid

Figure 26. EEPROM Interface Timing

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