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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETX15AEPGE 데이터시트(PDF) 72 Page - Texas Instruments |
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TNETX15AEPGE 데이터시트(HTML) 72 Page - Texas Instruments |
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72 / 79 page  TNETX15AE ADDRESS-LOOKUP DEVICE SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997 72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating conditions (see Figure 25) RESET (software) timing NO. MIN MAX UNIT 1 tw(RESET) Pulse duration, RESET low 3 µs 2 tsu(RESET) Setup time, RESET low before OSCIN ↑ 10 ns 3 th(RESET) Hold time, RESET low after OSCIN ↑ 12 ns OSCIN (Input) VCC(5V) (Input) VCC (Input) 1 RESET (Input) Signals† 2 3 Normal Operation † A pullup or active logic is required for each input to have known logic levels at all times, especially during reset when an I/O output is disabled. Figure 25. RESET (Software) Timing |
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