TNETX15AEPGE datasheet(11/79 Pages) TI1

11 / 79 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

general notation notes

Hexadecimal notation: Leading zero, followed by lower-case x, then hex digits, with space or punctuation

delimiters on both ends. A ...F are equivalent to a ...f (example: 0x12bc, 0x12BC0

Binary notation:

Trailing lower-case b after string composed of only 1 or 0, with space or punctuation

delimiters on both ends (example: 101011b).

Decimal notation:

A number composed of 0 ...9 digits with no prefix or suffix, with a space or

punctuation delimiters on both ends (example: 23965)

The least-significant bit in a register is the lowest number.

The least-significant byte of a multibyte value is the lowest number.

node address format (Ethernet native data format)

The node addresses are kept inside the TNETX15AE in Ethernet native data format. This is the same format

used when the address appears in the frame transmitted on the wire. Ethernet first transmits the least-significant

bit of a data byte on the wire. This makes the group/specific address appear in bit 40 (least-significant bit of

most-significant byte). The TNETX15AE address storage format is shown in the following:

BIT

BYTE (most-significant byte)

BYTE

Local/Universal

Address

Group/Specific

Address

DIO register access

There are only four byte-wide DIO registers that are hardware interfaced to the DIO interface. These registers

are treated like a pointer structure to locate internal registers, some of which are interfaced to external terminals

of the device (see Figure 2). The small number of registers actually on the DIO interface give the TNETX15AE

a small I/O map requirement when designing systems; also, it allows additional registers to be defined without

requiring the hardware interface to change.

SAD0–SAD1

SRNW

ESCS

SRDY

Auto-Increment

Internal

Registers

Internal RAM

MII Interface

EEPROM Interface

TNETX15AE

Access Register

SRAM Interface

Address-High

Address-Low

Data Register

Figure 2. DIO Access (Pointer) Registers

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