STM32F217VG datasheet(30/175 Pages) STMICROELECTRONICS

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Functional overview

STM32F21xxx

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DocID17050 Rev 9

management. It is hardware- or software-configurable through the option bytes.

The counter can be frozen in debug mode.

3.20.5

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

3.20.6

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

downcounter. It features:

•

A 24-bit downcounter

•

Autoreload capability

•

Maskable system interrupt generation when the counter reaches 0

•

Programmable clock source

3.21

Inter-integrated circuit interface (I²C)

Up to three I2C bus interfaces can operate in multimaster and slave modes. They can

support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the

7-bit dual addressing mode (as slave). A hardware CRC generation/verification is

embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

3.22

Universal synchronous/asynchronous receiver transmitters

(UARTs/USARTs)

The STM32F21x devices embed four universal synchronous/asynchronous receiver

transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous

receiver transmitters (UART4 and UART5).

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to

communicate at speeds of up to 7.5 Mbit/s. The other available interfaces communicate at

up to 3.75 Mbit/s.

USART1, USART2, USART3 and USART6 also provide hardware management of the CTS

and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication

capability. All interfaces can be served by the DMA controller.

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