STM32L151VD datasheet(71/140 Pages) STMICROELECTRONICS

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STM32L151xD STM32L152xD

Electrical characteristics

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6.3.5

External clock source characteristics

High-speed external user clock generated from an external source

IDD (RTC)

0.4

µA

IDD (LCD)

3.1

IDD (ADC)

(4)

1450

IDD (DAC)

(5)

340

IDD (COMP1)

0.16

IDD (COMP2)

Slow mode

Fast mode

IDD (PVD / BOR)

(6)

2.6

IDD (IWDG)

0.25

Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock

enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz

(range 3), fHCLK = 64kHz (Low power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for

each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.

HSI oscillator is OFF for this measure.

In low power sleep and run mode, the Flash memory must always be in power-down mode.

Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC

conversion (HSI consumption not included).

Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC

conversion of VDD/2. DAC is in buffered mode, output is left floating.

Including supply current of internal reference voltage.

Table 25.

Peripheral current consumption(1) (continued)

Peripheral

Typical consumption, VDD = 3.0 V, TA = 25 °C

Unit

Range 1,

VCORE=

1.8 V

VOS[1:0] =

Range 2,

VCORE=

1.5 V

VOS[1:0] =

Range 3,

VCORE=

1.2 V

VOS[1:0] =

Low power

sleep and

run

Table 26.

High-speed external user clock characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fHSE_ext

User external clock source

frequency

MHz

VHSEH

OSC_IN input pin high level voltage

0.7VDD

-VDD

VHSEL

OSC_IN input pin low level voltage

VSS

-0.3VDD

tw(HSE)

OSC_IN high or low time

tr(HSE)

tf(HSE)

OSC_IN rise or fall time

Cin(HSE)

OSC_IN input capacitance

2.6

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