| 전자부품 데이터시트 검색엔진 |
|
PRIXP425BD 데이터시트(PDF) 90 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
PRIXP425BD 데이터시트(HTML) 90 Page - Intel Corporation |
|
90 / 112 page ![]() Intel® IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications 90 Datasheet 5.5.2.4 MII NOTES: 1. These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay. NOTES: 1. These values satisfy the MII specification requirement of 10-ns setup and hold time. 2. Timing tests were performed with a 70-pF capacitor to ground. Figure 19. MII Output Timings Table 47. MII Output Timings Values Symbol Parameter Min. Max. Units Notes T1 Clock to output delay for ETH_TXDATA and ETH_TXEN. 017 ns 1 T2 ETH_TXDATA and ETH_TXEN hold time after ETH_TXCLK. 2 ns A9580-01 eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs T1 T2 Figure 20. MII Input Timings Table 48. MII Input Timings Values Symbol Parameter Min. Max. Units Notes T3 ETH_RXDATA and ETH_RXDV setup time prior to rising edge of ETH_RXCLK 5.5 ns 1, 2 T4 ETH_RXDATA and ETH_RXDV hold time after the rising edge of ETH_RXCLK 0 ns 1, 2 A9581-01 eth_rx_clk eth_rx_data[7:0] eth_rx_dv eth_crs T4 T3 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |