PRIXP425BD datasheet(29/112 Pages) INTEL

29 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Overview

Datasheet

The 32 x 32 signed multiply-accumulates (MIA) multiply a 32-bit, core-general register

(multiplier) and another 32-bit, core-general register (multiplicand) to produce a 64-bit product

where the 40 LSBs are added to the 40-bit accumulator. The 16 x 32 versions of the 32 x 32

multiply-accumulate instructions complete in a single cycle.

2.2.11

Performance Monitoring Unit (PMU)

The performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter.

The event counters can be programmed to monitor I-cache hit rate, data caches hit rate, ITLB hit

rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count.

2.2.12

Debug Unit

The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1 JTAG port

consists of a test access port (TAP) controller, boundary-scan register, instruction and data

registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#.

The debug unit — when used with debugger application code running on a host system outside of

the Intel XScale core — allows a program, running on the Intel XScale core, to be debugged. It

allows the debugger application code or a debug exception to stop program execution and redirect

execution to a debug-handling routine.

Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug

breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the

debugger application code can examine or modify the core’s state, coprocessor state, or memory.

The debugger application code can then restart program execution.

The debug unit has two hardware-instruction, break point registers; two hardware, data-breakpoint

registers; and a hardware, data-breakpoint control register. The second data-breakpoint register can

be alternatively used as a mask register for the first data-breakpoint register.

A 256-entry trace buffer provides the ability to capture control flow messages or addresses. A

JTAG instruction (LDIC) can be used to download a debug handler via the JTAG port to the

mini-instruction cache (the I-cache has a 2-Kbyte, mini-instruction cache to hold a debug handler).

PRIXP425BD 데이터시트(PDF) 29 Page - Intel Corporation