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HM5259165B 데이터시트(PDF) 29 Page - Elpida Memory

부품명 HM5259165B
상세설명  512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
PDF  63 Pages
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제조업체  ELPIDA [Elpida Memory]
홈페이지  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HM5259165B 데이터시트(HTML) 29 Page - Elpida Memory

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HM5259165B/HM5259805B/HM5259405B-75/A6
Data Sheet E0118H10
29
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less
than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z
before data input.
READ to WRITE Command Interval (1)
CLK
Command
Dout
in B2
in B3
READ WRIT
in B0
in B1
High-Z
Din
CL=2
CL=3
DQM,
DQMU
/DQML
Burst Length = 4
Burst write
READ to WRITE Command Interval (2)
CLK
Command
Dout
READ
WRIT
Din
CL=2
CL=3
DQM,
DQMU/DQML
High-Z
2 clock
High-Z
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must
be set High so that the output buffer becomes High-Z before data input.



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