LXT970ATC datasheet(45/74 Pages) INTEL

45 / 74 page

Dual-Speed Fast Ethernet Transceiver — LXT970A

Datasheet

3.3.7

Typical Application

Figure 21 on page 46 is typical interface circuitry of the LXT970A. The diagram groups similar

pins; it does not portray the actual chip pinout. The Media Independent Interface (MII) pins are at

the upper left. Hardware Control Interface pins are center left. The line interface pins for twisted-

pair and fiber are shown on the top and bottom right respectively.

The VCCD and VCCIO pins are at the bottom of the diagram. VCCT, VCCR, and VCCA are at the

center right. All VCC pins (except VCCIO) use a single power supply. VCCIO may be powered by

a 3.3V supply, and may be separately connected.

3.3.7.1

Voltage Divider For MF Inputs

The LXT970A requires an external voltage divider to provide optional (VMF2 and VMF3) multi-

level inputs to the Multi-Function (MF) pins. These voltage levels are designated as VMF1 - VMF4.

A single voltage divider may be used to drive the MF pins in designs using multiple PHYs. Figure

20 shows a voltage divider with three 1 k

Ω resistors configured in series between VCC and

Ground.

Figure 20. Voltage Divider

VMF4

VMF3

VMF2

+5V

VMF1

LXT970ATC 데이터시트(PDF) 45 Page - Intel Corporation