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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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RM0352 데이터시트(PDF) 52 Page - STMicroelectronics |
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RM0352 데이터시트(HTML) 52 Page - STMicroelectronics |
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52 / 138 page  ARM© dual timer module (SP804) RM0352 52/138 DocID024647 Rev 1 TIMCLK equals PCLK and TIMCLKENX equals one Figure 7 shows the case where TIMCLK is identical to PCLK and TIMCLKENX is permanently enabled. In this case, the counter is decremented on every TIMCLK edge. Figure 7. TIMCLK equals PCLK and TIMCLKENX equals one, clock example TIMCLK is less than PCLK and TIMCLKENX equals one Figure 8 shows the case where TIMCLK frequency is a submultiple of the PCLK frequency but the rising edges of TIMCLK are synchronous and balanced with PCLK edges. TIMCLKENX is permanently enabled. In this case, the counter is decremented on every TIMCLK rising edge. Figure 8. TIMCLK is less than PCLK and TIMCLKENX equals one, clock example Prescaler operation The prescaler generates a timer clock enable that is used to enable the decrementing of the timer counter at one of the following rates: • The effective timer clock rate where TIMCLK is qualified by TIMCLKENX • The effective timer clock rate divided by 16 • The effective timer clock rate divided by 256. |
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