RM0352 datasheet(28/138 Pages) STMICROELECTRONICS

28 / 138 page

Clock and reset management unit

RM0352

28/138

DocID024647 Rev 1

The field PROC_CLK_SEL is programmed to select the clock output from the 4-way

clock-switch. It can be programmed as in

Table 11.

Table 9. CRMU_CCR0

Address

Bit

Field name

Reset

R/W

Description

CRMU_BASE + 0x4

3:0

PROC_DIVFACTOR

(1)

4'b0000

R/W

Divide factor for the even clock divider

5:4

PROC_CLK_SEL

2'b00

R/W

Select for processor clock switch

7:6

HS_OSC_SEL

2'b00

R/W

Select internal 80 MHz clock oscillator as

source for high speed clock

LS_OSC_SEL

1'b1

R/W

Select internal 32 KHz clock oscillator as

source for 32 KHz clock

EXT_XO_EN

1'b0

R/W

Enable for external single ended clock

ANA_PD80M

1'b0

R/W

Enable for 80 MHz internal oscillator

ANA_CLK_OEN

1'b0

R/W

Output enable for IO6 in serial0 and serial1

modes

RESERVED

1'b1

R/W

The field PROC_DIVFACTOR is used to program the divide factor for the even divider of system clock (see

Section 5.2.1

on page 21). It can be programmed as per Table 10.

Table 10. Processor even divide factors

PROC divfactor[3:0]

Division

0000

0001

0010

0011

0100

0101

0110

0111

1000

Table 11. Processor clock selection

PROC select [5:4]

Processor clock

32 KHz/80 MHz/EXT_XO clock divided by 5

32 KHz/80 MHz/EXT_XO clock divided by

PROC_DIVFACTOR

32 KHz/80 MHz/EXT_XO clock divided by 3

32 KHz/80 MHz/EXT_XO clock

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