RM0352 datasheet(43/138 Pages) STMICROELECTRONICS

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RM0352

Watchdog timer (WDG)

137

7.2.5

Watchdog raw interrupt status register WDT_RIS

The WDTRIS register is the raw interrupt status register. This value is ANDed with the

interrupt enable bit from the control register to create the masked interrupt, which is passed

to the interrupt output pin.

Table 36 shows the bit assignment of the WDTRIS register.

Table 35. Watchdog raw interrupt status register WDT_RIS

7.2.6

Watchdog masked interrupt status register WDT_MIS

The WDT_MIS register is the masked interrupt status register. This value is the logical AND

of the raw interrupt status with the timer interrupt enable bit from the control register, and is

the same value which is passed to the interrupt output pin. This register is read-only, and all

bits are cleared by a reset.

Table 37. Watchdog masked interrupt status register WDT_MIS

WDT_RIS (WDT Base + 0x010)

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

WDTRIS

Table 36. WDT_RIS register bit fields

Bit field

Function

WDTRIS

Watchdog raw interrupt status bit

Reflect the status of interrupt status from the watchdog. Read-only bit. Write has no effect.

0b: watchdog interrupt is not set.

1b: watchdog interrupt is set.

WDT_MIS (WDT Base + 0x014)

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

987654321

RESERVED

WDTMIS

Table 38. WDT_MIS register bit fields

Bit field

Function

WDTMIS

Watchdog masked interrupt status bit

Masked value of watchdog interrupt status:

0b: watchdog line interrupt not active.

1b: watchdog line asserting interrupt. Read-only bit. Write has no effect.

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