RM0352 datasheet(67/138 Pages) STMICROELECTRONICS

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RM0352

System timer (SysTick)

137

System timer (SysTick)

9.1

About the SysTick

The Brain device also includes a system timer (SysTick) that can be used by an operating

system to ease porting from another platform. The SysTick can be polled by software or can

be configured to generate an interrupt. The SysTick interrupt has its own entry in the vector

table and therefore can have its own handler. For more details on SysTick system timer, see

“ARMv6-M Architecture Reference Manual”.

9.2

SysTick registers

The SysTick is configured through the four registers described in

Table 65. Those registers

are located in the System Control Space (SCS) memory area of the Cortex-M0 subsystem.

The SysTick base address is 0xE000_E010.

Table 65. SysTick registers

Address

Name

Type

Reset value

Description

SysTick base + 0x000

SYST_CSR

0x00000004

SysTick control and status.

Basic control of SysTick e.g. enable, clock source,

interrupt or poll. See

Section 9.3.1: SysTick control

and status register (SYST_CSR) on page 68.

SysTick base + 0x004

SYST_RVR

SysTick reload value.

Value to load current value register when 0 is

reached. See

Section 9.3.2: SysTick reload value

SysTick base + 0x008

SYST_CVR

SysTick current value. See

Section 9.3.3: SysTick

current value register (SYST_CVR) on page 69.

SysTick base + 0x00C

SYST_CALIB

0x80000000

SysTick calibration value.

Might contain the number of ticks to generate a 10

ms interval and other information, depending on

implementation. See

Section 9.3.4: SysTick

calibration value register (SYST_CALIB) on

page 69.

SysTick base + 0x010

to 0x0FF

RESERVED

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