Interfacing with asynchronous memory

AN2647

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1.4

Executing code from external SRAM vs. internal Flash

The EMI bus is designed for supporting external data storage. However, the CPU can also

fetch and execute instruction codes from external memory; the performance would be lower

when compared to execution from internal Flash. Please note the Prefetch Queue and

Branch Cache are dedicated for internal Flash memory and are not available for external

code fetch.

There is a four-word buffer on the AHB bus to facilitate the external code fetch. The buffer is

flushed whenever there is a non-sequential fetch, this results in a series of burst fetch

requests to the EMI bus to fill up the buffer. Using memory that has burst mode or page

mode would enhance the CPU performance.

The ARM instructions are 32-bits, to fetch an instruction the EMI in general generates 1

burst mode read request, of length 4, when the EMI bus is 8-bit wide and 2 read requests for

16-bit bus. Table 6 below lists the number of BCLK clocks needed to fetch an instruction

sequentially from external memory and internal Flash. The 8-bit non-multiplexed EMI bus is

configured for page mode or fast SRAM access, which takes one BCLK clock to read a byte.

The 16-bit multiplexed bus is configured for the shortest possible read cycle and takes 3

BCLK clocks to read a halfword. As shown in the table, the CPU takes more time to fetch an

instruction from external memory and results in lower performance.

SCU_CLKCNTR 18:17

EMIRatio

00

BCLK=HCLK

(96 MHz)

01

BCLK=HCLK

(96 MHz)

SCU_SRC0

8

EMI_ALE_LNGT

0

ALE length=1

0Don’t care

7

EMI_ALE_POLR

1

ALE polarity-active

high

0Don’t care

6

EMI_MULTIPLEXED

0

Multiplexed mode

1

Non-Multiplexed mode

Table 5.

EMI Bus configuration examples for asynchronous memory devices

Configuration

register

Register bit

Multiplexed 16-bit bus

Non-Multiplexed 8-bit bus

Bit

Name

Bit

value

Function

Bit

value

Function

Table 6.

Number of BCLK clocks required to fetch a sequential instruction

Program code

Read bus cycle

length

#of bus cycle per

instruction

#of BCLK

between cycles

#of BCLK per

instruction fetch

External memory 8-

bits non-mux bus

(page mode)

1 BCLK Clock

4

2

(1BCLK*4)+2=6

External memory 16-

bit mux bus (SRAM)

3 BCLK Clock

2

2

(3BCLK+2)*2=10

Internal Flash

memory 32-bit bus

1 BCLK Clock

1

0

1