Interfacing with synchronous memory

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2.2

Connecting the EMI bus to a PSRAM

The EMI bus operates in 16-bit multiplexed mode. The PSRAM itself has a non-multiplexed

bus interface with separate address and data bus inputs. However, the ADV# signal in the

PSRAM is able to latch the address internally and the address is not required to stay

throughout the bus cycle. The EMI's multiplexed bus takes advantage of this feature, it

drives the address and the ADV# in the address phase of the bus cycle. After the address is

latched by PSRAM, the EMI then drives data out in a write cycle or floats the bus in a read

cycle.

Figure 11. shows the EMI bus connection to a PSRAM. Port 7 drives the non-multiplexed

address A[21:16]. A[23:22] pins are not needed, the P5.1 and P6.0 pins are configured to

drive the chip select signals CS1 and the CRE signal respectively. CRE (Configuration

Register Enable) must be high when the EMI is accessing the configuration registers of the

PSRAM. The CS1 is generated automatically by the EMI when accessing the PSRAM, but

CRE is a software controlled GPIO signal and must be set before you can access the

PSRAM registers. Please note no logic gate is needed in the EMI/PSRAM interface.

Figure 11.

Glue-less" bus interface: connecting the PSRAM to the EMI bus