AN2647

Interfacing with synchronous memory

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EMI read and write asynchronous bus cycle

The EMI configurations in Table 8 will generate the write and read timing as shown in

Figure 14. The EMI_ALE signal, which indicates the start of a bus cycle, is connected to the

MT45W4M ignores the inputs on its address pins after the address latching. This allows the

Figure 14.

EMI bus write and read bus cycles in asynchronous mode

Note:

For your reference an asynchronous software example is delivered with this application

note.