Interfacing with synchronous memory

AN2647

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EMI burst read bus cycle

In synchronous mode, the PSRAM latches the address at the rising clock edge while ALE is

low. The write signal WEn must be high when the address is sampled to start a read bus

cycle. The STR91xFA always reads in 16-bit with the UB/LB byte select signals staying low

for the entire cycle. For the initial access of the read cycle, the PSRAM is set up for fixed

latency with a latency counter value of 4. The read wait state WSTRD in the EMI is set up to

5 to match the PSRAM timing. Burst read cycle starts after the first initial access and the

PSRAM is driving data out every BCLK clock until the end of the chip select signal CSx. The

timing in Figure 15. shows a burst read cycle initiated by STR91xFA while executing a Load

Multiple instruction.

Figure 15.

EMI read bus cycle in burst mode

SCU_GPIOOUT7

15:0

Output Function

0x0AAA

Set Port 7 pins P7.5-P7.0 as A[21:16]

SCU_GPIOOUT6

15:0

Output Function

0x0001

P6.0 as GPIO out

SCU_GPIOOUT5

15:0

Output Function

0x0C00

Set P5.5 as CS1

Table 10.

EMI and port register config. for PSRAM sync mode (80 MHZ) BCLK)

EMI configuration

register

Register bit

Multiplexed 16-bits asynchronous mode

Bit

Name

Bit

value

Function