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AN3255

I2C memory addressing

Doc ID 17784 Rev 1

19/24

Appendix A

I2C memory addressing

To start communicating with the CR14, the bus master initiates a START condition and

sends 8 bits (with Most Significant Bit first) on the serial data line SDA. These bits contain

the Device Select Code (7 bits) and the RWbar bit.

According to the I2C bus definition, the seven Most Significant Bits of the Device Select

Code are the Device Type Identifier. For the CR14 these bits definition is given in Table 7.

The 8th bit is the Read/Write bit (RWbar). It is set to ‘1’ for I2C read and to ‘0’ for I2C write

operations.

If the data sent by the bus master matches the Device Select Code of the CR14, it returns

an acknowledgement on the bus during the 9th bit time. The CR14 device generates a

NACK if its Device Select Code does not correspond to the data sent. It deselects himself

from the bus and goes in standby mode.

Refer to the CR14 datasheet for details regarding the CR14 I2C protocol, and to the STM8S

reference manual for a functional description on I2C peripheral.

Table 7.

Device Select code

Device Code

Chip Enable

RWbar

CR14

select

RWbar

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