PM0044 datasheet(19/162 Pages) STMICROELECTRONICS

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PM0044

STM8 memory interface

Doc ID 13590 Rev 3

19/162

4.3

Memory interface architecture

The STM8 uses a Harvard architecture, with separate program and data memory buses.

However, the logical address space is unified, all memories sharing the same 16-Mbytes

space, non-overlapped. The memory interfaces are shown in Figure 4. It consists of two

buses: address, data, read/write control signal (R/W) and memory acknowledge signal

(STALL).

The STALL acknowledge signal makes the CPU compatible with slow serial or parallel

memory interfaces. When the memory interface is slow the CPU waits the memory

acknowledge before executing the instruction. So in such a case, the instruction CPU cycle

time is prolonged compare to the value given in this manual.

The program memory bus is 32-bit wide, allowing the fetch of most of the instructions in one

cycle.

As the address space is unified, the architecture allows data to be stored also in the Flash

memory and program to be fetched also from RAM (data bus). In this later case the

performance is impacted, besides the fact that data and fetch operation share the same bus,

the instructions will be fetched one byte at a time, thus taking longer (1 cycle /byte).

Figure 4.

Memory Interface Architecture

PCE PCH

PCL

PROGRAM COUNTER

Data@E

Data@E0:H:L

0x00

"LDF" INSTRUCTION

@DATABUS

RAM FETCH INSTRUCTION

CPU

Memory Interface (RAM)

STALL

A15..0

D7..0

R/W

Memory Interface (Flash)

STALL

A23..0

D31..0

@DATABUS

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