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ST9 USER GUIDE

3.6.1.1 Clock Multiplier

The Clock Multiplier is a part of the Figure 26.

The advantage of the Clock Multiplier is that it can produce a variable clock frequency de-

pending on the needs of the CPU.

Since the input clock to the PLL circuit requires a 50% duty cycle for correct operation, the di-

vide by two should be enabled (DIV2 bit of MODER register set) if the PLL is enabled. It is nec-

essary when a crystal oscillator is used, or when the external clock generator does not provide

a 50% duty cycle. In practice, the divide-by-two is virtually always used in order to ensure a

50% duty cycle signal to the PLL multiplier circuit.

The Clock Multiplier output is one of the CLOCK2, CLOCK2/16 or CLOCK2*PLLMUL/(DX+1)

(PLLMUL is the PLL multiplier coefficient) frequencies.

The two frequencies CLOCK2 and CLOCK2/16 are for low power consumption or reduce

power consumption, depending on the Wait For Interrupt instruction (refer to the flow chart

Figure 25).

The PLL has four clock multiplier factors (6,8,10 and 14) controlled by the two bits MX0 and

MX1 in the PLLCONF register. The clock divider is controlled by three bits DX0:2 in the

PLLCONF register for seven rates which are 1/(DX+1). Setting DX2:0=7 turns OFF the PLL to

reduce consumption.

When you switch on the PLL, you have to allow a delay for the PLL to lock.

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