ST9 datasheet(77/146 Pages) STMICROELECTRONICS

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77/146

ST9 USER GUIDE

In addition to providing output signals, the timers can generate so-called “internal events” that

can be used to synchronize other internal peripherals such as the DMA and the Analog to Dig-

ital Converter. Not all peripherals to be synchronized can be connected to just any MFT. For

each ST9 variant, the connection between each MFT and the other peripheral is unique. Refer

to the corresponding datasheet for more information.

The second block diagram represents the counter, the capture and compare registers, the re-

load logic and the associated configuration and status registers. The interrupt and DMA blocks

are not represented.

Figure 35

. MFT Simplified Block Diagram

In the above diagrams, the interrupt and DMA logic are not represented. They obey the gen-

eral interrupt and DMA rules described earlier, and are controlled by three registers.

The Interrupt Vector Register controls the location of the interrupt vectors in program memory.

They must be located at addresses that are multiples of 8.

VR02111J

2 bits of

FLAGR

(result:)

6 bits of

TMR

1 bit of TCR

1 bit of CICR

Compare 1 Register

Compare 0 Register

Compare Logic

16-bit Counter

with Comparator

Capture/Load Register 0

Capture/Load Register 1

Load/Capture/Monitor

Logic

Counter

Enable

1 bit of TCR

(OVF/UNF)

(result:)

2 bits of

FLAGR

Clock

U/D

Clear

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