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ST9 USER GUIDE

3.1.7.4 Data Segment

Data uses the page mechanism to address the 4 Mbytes of memory.

To authorize data coming from different 64-Kbyte segments, a set of 4 Data Page Registers

(DPR0 to DPR3) allows you to address 16 Kbytes per register (see Figure 13). The DPR is se-

lected with the 2 high-order bits of the 16-bit data address:

DPR0: from 0000h to 3FFFh (b15-b14=00)

DPR1: from 4000h to 7FFFh (b15-b14=01)

DPR2: from 8000h to BFFFh (b15-b14=10)

DPR3: from C000h to FFFFh (b15-b14=11)

After you select the DPR, the 8-bit value of the selected DPR register is used to extend the 14

remaining bits of the address to 22 bits.

For example, if DPR0 equals 20h and DPR1 equals 2h, each memory access in the range of

0000h to 3FFFh uses the DPR0 page and addresses data from 080000h to 083FFFh, and

each memory access in the range of 4000h to 7FFFh uses the DPR1 page and addresses

data from 008000h to 00BFFFh (see Figure 13). For example:

16-bit address = 0010 0101 1010 0101 = 25A5h

0000h < 25A5h < 3FFFh

DPR0 is selected, so the 6 high-order bits are equal to 20h

22-bit address = 0010 0000 10 0101 1010 0101

DPR0 value, 14 LSB of the 16-bit address

= 00 1000 0010 0101 1010 0101 = 0825A5h

With this mechanism, if the 16-bit addresses are different only on the 2 highest bits and if all

the DPR registers selected with these two bits have the same value, the resulting 22-bit ad-

dress will be the same.

Four pages of 16Kbyte of data memory are enough for many applications and allow you to use

data from different segments without costing additional CPU cycles. With four DPRs, you can

access up to 64K (4 x 16K) of data without changing the DPR values. Data can be variables

stored in RAM or constants stored in program ROM.

The four DPR registers are located in the MMU register page (page 21 of register group F). If

you use them frequently, you can relocate them to register group E, by programming bit 5 of

the EMR2 register (R246 in page 21). This prevents you from having to switch to the MMU

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