ST9 datasheet(79/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

Figure 38

. MFT Interrupt and DMA Control Register

The Input and Output Control Register has only two active bits. They are used to internally

connect the Output A of each MFT to its own Input A. One bit does this connection for all even-

numbered MFTs, and the other for all odd-numbered MFTs.

Figure 39

. MFT I/O Control Register

4.4.1 Generating Two Pulse Width Modulated Waves with One MFT

4.4.1.1 Description Example

The Multifunction Timer is used here as a double pulse-width modulator. It is also possible to

have a single PWM output if needed. Let’s look at a simplified block diagram of the MFT

showing only the functional blocks that are actually used. See Figure 40.

This is possible using the two comparators that simultaneously compare each capture register

with the free-running counter. When the counter overflows, it is reloaded with the contents of

the Load Register 0. At that time, both outputs are reset.

When the value of the counter becomes equal to one of the compare registers, a pulse is sent

to the output flip-flop of the corresponding side, thus setting the output. So the low time is the

time between the counter overflow and the comparison. The high time is the remainder of the

period.

IDCR (R243, Page 9, MFT 0) (R247, Page 9, MFT 1)

Interrupt/DMA Control Register

Interrupt/DMA Priority Level

CPE CME DCTS DCTD SWEN PL2 PL1 PL0

SC1

SC0

IOCR (R248)

I/O Connection Register

IOCR (R248)

TxINA and TxOUTA

Internally connected or not

for each even MFT.

TxINA and TxOUTA

Internally connected or not for each odd MFT.

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