RM0312 datasheet(52/275 Pages) STMICROELECTRONICS

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Interrupt controller (ITC)

RM0312

52/275

DocID022352 Rev 3

5.9.4

External interrupt control register 2 (EXTI_CR2)

Address offset: 0x01

Reset value: 0x00

654

3210

P7IS[1:0]

P6IS[1:0]

P5IS[1:0]

P4IS[1:0]

Bits 7:6 P7IS[1:0]: Portx bit 7 external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They

define the sensitivity of the bit 7 of Port A, B, and/or D external interrupts.

00: Falling edge and low level

01: Rising edge only

10: Falling edge only

11: Rising and falling edge

Bits 5:4 P6IS[1:0]: Portx bit 6 external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They

define the sensitivity of the bit 6 of Port A, B, and/or D external interrupts.

00: Falling edge and low level

01: Rising edge only

10: Falling edge only

11: Rising and falling edge

Bits 3:2 P5IS[1:0]: Portx bit 5 external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They

define the sensitivity of the bit 5 of Port B, and/or D external interrupts.

00: Falling edge and low level

01: Rising edge only

10: Falling edge only

11: Rising and falling edge

Bits 1:0 P4IS[1:0]: Portx bit 4 external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They

define the sensitivity of the bit 4 of Port A, B, and/or D external interrupts.

00: Falling edge and low level

01: Rising edge only

10: Falling edge only

11: Rising and falling edge

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