RM0312 datasheet(78/275 Pages) STMICROELECTRONICS

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General purpose I/O ports (GPIO)

RM0312

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DocID022352 Rev 3

10.3.2

Output modes

Setting the DDRx bit selects output mode. In this mode, writing to the ODR bits applies a

digital value to the I/O through the latch. Reading IDR bit returns the digital value from the

corresponding I/O pin. Using the CR1, CR2 registers, different output modes can be

configured by software: Push-pull output, Open-drain output.

Refer to Section 10.8: Output mode details on page 79 for more information.

10.4

Reset configuration

All I/O pins are generally input floating under reset (i.e. during the reset phase) and at reset

state (i.e. after reset release). However, a few pins may have a different behavior. Refer to

the datasheet pinout description for all details.

10.5

Unused I/O pins

Unused I/O pins must not be left floating to avoid extra current consumption. They must be

put into one of the following configurations:

•

connected to VDD or VSS by external pull-up or pull-down resistor and kept as input

floating (reset state),

•

configured as input with internal pull-up/down resistor,

•

configured as output push-pull low.

The I/O ports not present on smaller packages are automatically configured by hardware

(unless otherwise specified in the datasheet). As a consequence, no configuration is

required on these I/O ports. The bits corresponding to these ports in the configuration

registers Px_ODR, PxDDR, PxCR1 and PxCR2 can be written, but this will have no effect.

The value read in the corresponding bits of the PxIDR register will be '0'.

10.6

Low power modes

Table 20. Effect of low power modes on GPIO ports

Mode

Description

Wait

No effect on I/O ports. External interrupts cause the device to exit from Wait

mode.

Halt

No effect on I/O ports. External interrupts cause the device to wakeup from

Halt mode.

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