RM0312 datasheet(108/275 Pages) STMICROELECTRONICS

108 / 275 page

16-bit general purpose timer (TIM2/TIM3)

RM0312

108/275

DocID022352 Rev 3

17.3.1

Reading and writing to the 16-bit counter

There is no buffering when writing the counter. Both TIMx_CNTRH and TIMx_CNTRL can

be written at any time, so it is suggested not to write a new value into the counter while it is

running to avoid loading a wrong intermediate content.

An 8-bit buffer is implemented for the read. The user must read the MS byte first, then the

LS byte value is buffered automatically, as described in Figure 21. This buffered value

remains unchanged until the 16-bit read sequence is completed.

Note:

Do not use the LDW instruction to read the 16-bit counter, because it reads the LS byte first,

and would return a wrong result.

Figure 21. 16-bit read sequence for the counter (TIMx_CNTR)

17.3.2

Write sequence for 16-bit TIMx_ARR register

16-bit values are loaded in the TIMx_ARR

performed by two write instructions, one for each byte. The MS byte must be written first.

The shadow register update is blocked as soon as the MS byte has been written, and stays

blocked until the LS byte has been written. Do not use the LDW instruction, as this writes

the LS byte first, and would produce wrong results in this case.

17.3.3

Prescaler

The prescaler is based on a 7-bit counter controlled through a 3-bit register (in TIMx_PSCR

counter clock frequency by 1, 2, 4, 8, 16, 32, 64 or 128.

The counter clock frequency is calculated as follows:

fCK_CNT = fCK_PSC/2(PSCR[2:0])

The new prescaler value is taken into account in the following period (after the next counter

update event).

is buffered

Read

At t0

Read

Returns the buffered

LS Byte value at t0

At t0 +Dt

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS byte

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