RM0312 datasheet(119/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

Figure 36. Control circuit in trigger mode

Trigger reset mode

The counter and its prescaler can be re-initialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is

generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the up-counter is cleared in response to a rising edge on TI1 input:

•

Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=0b0000). The capture

prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits

select the input capture source only, and do not need to be configured either. Write

CC1P=0 in TIMx_CCER1 register to validate the polarity (and detect rising edges only).

•

Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=0b101 in TIMx_SMCR register.

•

Start the counter by writing CEN=1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until TI1 rising

edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the

trigger flag is set (TIF bit in the TIMx_SR1 register) and an interrupt request can be sent if

enabled (depending on the TIE in TIMx_IER register).

The following figure shows this behaviour when the auto-reload register TIMx_ARR=36h.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the

resynchronization circuit on TI1 input.

Figure 37. Control circuit in trigger reset mode

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER

35 36 37 38

TI2

CNT_EN

TIF

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER

01 02 03 00 01 02 03

32 33 34 35 36

TI1

TIF

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