RM0312 datasheet(243/275 Pages) STMICROELECTRONICS

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RM0312

Universal synchronous/asynchronous receiver transmitter (USART)

249

21.6

USART registers

21.6.1

Status register (USART_SR)

Address offset: 0x00

Reset value: 0xC0

654

3210

TXE

RXNE

IDLE

rc_w0

rrrr

Bit 7 TXE: Transmit data register empty

This bit is set by hardware when the content of the TDR register has been transferred into the shift

to the USART_DR register.

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Bit 6 TC: Transmission complete

TC bit is set by hardware if the transmission of a frame containing data is complete and TXE bit is set.

An interrupt is generated if TCIEN=1 in the USART_CR2 register.

TC bit is cleared either by a software sequence (a read to the USART_SR register followed by a write

to the USART_DR register), or by programming the bit to ‘0’. This clear sequence is recommended

only for multibuffer communications.

0: Transmission is not complete

1: Transmission is complete

Bit 5 RXNE: Read data register not empty

This bit is set by hardware when the content of the RDR shift register has been transferred to the

USART_DR register. An interrupt is generated if RIEN=1 in the USART_CR2 register. It is cleared by

a read to the USART_DR register.

0: Data is not received

1: Received data is ready to be read.

Bit 4 IDLE: IDLE line detected (1)

This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIEN=1 in

the USART_CR2 register. It is cleared by a software sequence (a read to the USART_SR register

followed by a read to the USART_DR register).

0: No Idle Line is detected

1: Idle Line is detected

Bit 3 OR: Overrun error(2)

This bit is set by hardware when the word currently being received in the shift register is ready to be

transferred into the RDR register while RXNE=1. An interrupt is generated if RIEN=1 in the

USART_CR2 register. It is cleared by a software sequence (a read to the USART_SR register

followed by a read to the USART_DR register).

0: No Overrun error

1: Overrun error is detected

Bit 2 NF: Noise flag (3)

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software

sequence (a read to the USART_SR register followed by a read to the USART_DR register).

0: No noise is detected

1: Noise is detected

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