RM0319 datasheet(351/368 Pages) STMICROELECTRONICS

351 / 368 page

RM0319

DMA controller (DMAC)

Doc ID 022640 Rev 3

351/368

DMA controller (DMAC)

This chapter focuses on DMAC functionality and operation.

For technical details about the programmable registers related to the DMAC, refer to the

DMAC registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

36.1

Overview

The DMA controller is able to service up to 8 independent DMA channels for sequential data

transfers between single source and destination (memory-to-memory, memory-to-

peripheral, peripheral-to-memory, and peripheral-to-peripheral).

36.2

Main features

●

Each DMA channel can support a unidirectional transfer, with internal 16-words FIFO

per channel.

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16 peripheral DMA request lines, where each peripheral connected to the DMAC can

assert either a single DMA request or a Burst DMA request (with programmable size to

increase data transfer effectiveness).

●

Hardware priority (0 the highest to 7 the lowest) for each DMA channel to manage

requests from more than 1 channel at the same time.

●

Scatter or gather DMA support through the use of linked lists.

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An AHB slave acting as programming interface to access to DMA control registers

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Two AHB masters for data transfer following a DMA request

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32-bit AHB master bus width, supporting 8-/16-/32-bit wide transactions

●

Support both big-endian and little-endian (little endian is the default mode on DMAC

reset)

●

Separate and combined DMA error and DMA count interrupt requests, with three

interrupt request signals (DMACINTTC, DMACINTERR and DMACINTR)

●

Interrupt masking and raw interrupt status (prior to masking)

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