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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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RM0319 데이터시트(PDF) 352 Page - STMicroelectronics |
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RM0319 데이터시트(HTML) 352 Page - STMicroelectronics |
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352 / 368 page  DMA controller (DMAC) RM0319 352/368 Doc ID 022640 Rev 3 36.3 Functional description Figure 116. DMAC block diagram For the DMA channel assignment, please refer to the DMA_CHN_CFG register description in the System configuration registers (MISC) section of RM0321: SPEAr320S address map and registers. 36.3.1 Signal interfaces The DMAC directly interfaces with the signals summarized in Table 124. A functional diagram of these signal interfaces is given in Figure 117. Figure 117. DMAC signal interface diagram DMA REQUEST AND RESPONSE BLOCK AHB SLAVE INTERFACE CHANNEL 0 CHANNEL 1 CHANNEL 7 A R B I T E R A R B I T E R AHB MAST I/F AHB MAST I/F AHB MASTER 1 AHB MASTER 2 AHB BUS DMACTC[15:0] DMACCLR[15:0] DMACSREQ[15:0] DMACBREQ[15:0] DMACLSREQ[15:0] DMACLBREQ[15:0] AHB master #1 AHB master #2 AHB slave DMA response DMA request Interrupt request (to interrupt controller) DMAC |
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