UPD75402ACT datasheet(23/48 Pages) NEC

23 / 48 page

µPD75402A(A)

RESET FUNCTION

When a low level signal is input to the RESET input pin, the state changes to the system reset. Table 8-1

shows the statuses of the hardware.

When the RESET signal rises from the low level to the high level, the reset state is released. The three low-

order bits of the reset vector table whose address is 000H is set in bits 10 to 8 of the program counter (PC)

and the contents of the reset vector table whose address is 001H is set in bits 7 to 0 of the PC. The program

branches to that address and starts execution, i.e., the reset start address is programmable.

Initialize contents of registers in a program if necessary.

The RESET pin connects to the Schmitt-trigger circuit whose threshold level has hysteresis in the chip. This

pin is also connected to the noise eliminator using an analog delay to eliminate narrow noise and prevent

errors caused by noise. (See Fig. 8-1.)

For the power-on reset operation, be sure to allow sufficient time for oscillation to settle between power

on and acceptance of the reset signal (see Fig. 8-2).

Fig. 8-1 Acceptance of the Reset Signal

RESET

Analog

delay

Analog

delay

Analog

delay

Content of the reset

vector table is set

to the PC

(the initialization of the PC).

The instruction which

is stored at the reset

branch address is executed.

Elimination

as noise.

This low level

signal is accepted

as the reset signal.

The reset is

released.

Fig. 8-2 Power-On Reset Operation

VDD

RESET

Oscillation

settling time

Analog

delay

The reset

is released.

Content of the reset vector

table is set to the PC

(the initialization of the PC).

The instruction which is stored

at the reset branch address is

executed.

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