| 전자부품 데이터시트 검색엔진 |
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UPD75402ACT 데이터시트(PDF) 33 Page - NEC |
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UPD75402ACT 데이터시트(HTML) 33 Page - NEC |
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33 / 48 page ![]() 33 µPD75402A(A) Serial transfer operation Three-wire serial I /O mode (SCK ··· Internal clock output): Note RL and CL are the resistance and capacitance of the SO output line load respectively. Three-wire serial I/O mode (SCK ··· External clock input): Parameter SCK cycle time SCK high/low level width SI setup time (referred to SCK ↑) SI hold time (referred to SCK ↑) Delay from SCK ↓ to SO output Note RL and CL are the resistance and capacitance of the SO output line load respectively. Parameter SCK cycle time SCK high/low level width SI setup time (referred to SCK ↑) SI hold time (referred to SCK ↑) Delay from SCK ↓ to SO output Symbol tKCY2 tKL2 tKH2 tSIK2 tKSI2 tKSO2 VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V RL = 1 k Ω, CL = 100 pF Note Typ. Max. 250 1000 Unit ns ns ns ns ns ns ns ns Min. 1600 3800 tKCY1/2 – 50 tKCY1/2 – 150 150 400 0 0 Symbol tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Min. 800 3200 400 1600 100 400 0 0 Typ. Max. 300 1000 Unit ns ns ns ns ns ns ns ns Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V RL = 1 k Ω, CL = 100 pF Note VDD = 4.5 to 6.0 V |
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