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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD75P4308GS 데이터시트(PDF) 5 Page - NEC |
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UPD75P4308GS 데이터시트(HTML) 5 Page - NEC |
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5 / 60 page  µPD75P4308 5 2. BLOCK DIAGRAM BIT SEQ. BUFFER (16) PORT0 P00-P03 4 PORT1 PORT2 4 PORT3 P30/MD0- P33/MD3 4 PORT5 P50/D4- P53/D7 4 PORT6 P60/KR0/D0- P63/KR3/D3 4 Vss VDD RESET VPP CPU CLOCK Φ STAND BY CONTROL X2 X1 CLOCK GENERATOR CLOCK DIVIDER CLOCK OUTPUT CONTROL fx/2 N PCL/P22 GENERAL REG. RAM DATA MEMORY 256 × 4 BITS BANK SP (8) CY ALU PROGRAM COUNTER PROM PROGRAM MEMORY 8192 × 8 BITS DECODE AND CONTROL BASIC INTERVAL TIMER/ WATCHDOG TIMER TI0/TI1/P13 INTBT PTO0/P20 INTT1 CLOCKED SERIAL INTERFACE SI/P03 INTERRUPT CONTROL INT0/P10 SO/SB0/P02 SCK/P01 INT1/P11 INT2/P12 INT4/P00 KR0/P60/D0- KR3/P63/D3 KR4/P70- KR7/P73 8 PORT7 P70-P73 4 PORT8 P80, P81 2 P10-P13 4 P20-P23 INTCSI CASCADED 16-BIT TIMER/ EVENT COUNTER 8-BIT TIMER/EVENT COUNTER#0 8-BIT TIMER/EVENT COUNTER#1 INTT0 TOUT0 TOUT0 SBS 4 4 4 4 4 4 4 2 PTO1/P21 |
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