| 전자부품 데이터시트 검색엔진 |
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UPD75P4308GS 데이터시트(PDF) 9 Page - NEC |
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UPD75P4308GS 데이터시트(HTML) 9 Page - NEC |
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9 / 60 page ![]() µPD75P4308 9 3.3 Pin I/O Circuits The equivalent circuits for the µPD75P4308’s pin are shown in simplified schematic diagrams below. (1/2) IN VDD P-ch N-ch VDD P-ch N-ch OUT Data Output disable IN VDD P-ch IN/OUT P.U.R. enable Data P.U.R. Type D Output disable P.U.R.: Pull-Up Resistor Type A VDD P-ch P.U.R. enable P.U.R. P.U.R. : Pull-Up Resistor IN VDD P-ch IN/OUT P.U.R. enable Data P.U.R. Type D Output disable P.U.R.: Pull-Up Resistor Type B CMOS standard input buffer Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). Schmitt trigger input with hysteresis characteristics. TYPE A TYPE D TYPE E-B TYPE B TYPE B-C TYPE F-A Schmitt trigger input with hysteresis characteristics. |
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