UPD75P4308GS datasheet(8/60 Pages) NEC

8 / 60 page

µPD75P4308

External event pulse input to timer/event counter

Timer/event counter output

Clock output

Serial clock I/O

Serial data output

Serial data bus I/O

Serial data input

Edge-triggered vectored interrupt input

(triggered by both rising and falling edges).

3.2 Non-port Pins

Pin name

I/O

Alternate

Function

After

I/O Circuit

function

reset

typeNote 1

TI0/TI1

Input

P13

Input

-C

PTO0

Output

P20

Input

E-B

PTO1

P21

PCL

P22

SCK

I/O

P01

Input

<F>-A

SO/SB0

P02

<F>-B

Input

P03

-C

INT4

P00

—

INT0

Input

P10

—

-C

INT1

P11

INT2

P12

KR0 to KR3

Input

P60/D0 to

Input

<F>-A

P63/D3

KR4 to KR7

P70 to P73

Input

—

——

—

RESET

Input

—

MD0 to MD3

Input

P30 to P33

Input

E-B

D0 to D3

I/O

P60/KR0 to

Input

<F>-A

P63/KR3

D4 to D7

P50 to P53

M-E

VPPNote 2

——

VDD

——

VSS

——

Notes 1. Circuit types in brackets indicate Schmitt trigger input.

2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin.

Noise elimination

circuit appended/

asynchronous

selectable

Edge-triggered vectored interrupt

input (detected edge is selectable).

Noise elimination circuit selectable

in INT0/P10.

Asynchronous

Rising edge-triggered test input

Falling edge-triggered testable input

Ceramic/crystal connection for system clock oscillation.

If using an external clock, input it to X1 and input the

inverted clock to X2.

System reset input

Mode selection for program memory (PROM) write/

verify.

Data bus pin for program memory (PROM) write/verify.

Program supply voltage in program memory (PROM)

write/verify mode.

In normal operation mode, connect directly to VDD.

Apply +12.5 V in PROM write/verify mode.

Positive power supply

Ground

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