LTC1736 datasheet(26/28 Pages) LINER

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LTC1736

APPLICATIO S I FOR ATIO

Figure 10. LTC1736 Layout Diagram

COSC

RUN/SS

ITH

FCB

SGND

PGOOD

SENSE –

SENSE +

VFB

VOSENSE

VID0

VID1

BOOST

VIN

INTVCC

PGND

EXTVCC

VIDVCC

VID4

VID3

VID2

LTC1736

1000pF

47pF

CC1

COSC

CC2

CSS

4.7

µF

EXTERNAL EXTVCC

CONNECTION

CIN

–

RSENSE

COUT

VIN

VOUT

1736 F10

SENSE + SENSE –

HIGH CURRENT PATH

1736 F11

CURRENT SENSE

RESISTOR

(RSENSE)

Figure 11. Kelvin Sensing RSENSE

2. Does the VOSENSE pin connect as close as possible to

the load? The optional 50pF to 100pF capacitor from

VFB to SGND should be as close as possible to the

LTC1736.

3. Are the SENSE – and SENSE + leads routed together with

minimum PC trace spacing? The filter capacitor be-

tween SENSE + and SENSE – should be as close as

possible to the LTC1736. Ensure accurate current sens-

ing with kelvin connections as shown in Figure 11.

Series resistance can be added to the SENSE lines to

increase noise rejection.

4. Does the (+) terminal of CIN connect to the drain of the

topside MOSFET(s) as closely as possible? This capaci-

tor provides the AC current to the MOSFET(s).

5. Is the INTVCC decoupling capacitor connected closely

between INTVCC and the power ground pin? This ca-

pacitor carries the MOSFET driver peak currents. An

additional 1

µF ceramic capacitor placed immediately

next to the INTVCC and PGND pins can help improve

noise performance.

6. Keep the switching node (SW), Top Gate node (TG) and

Boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on the

“output side” (Pins 13 to 24) of the LTC1736 and

occupy minimum PC trace area.

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