MEC1322 datasheet(259/456 Pages) MICROCHIP

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DS00001719D-page 259

MEC1322

21.4

Interface

This block is designed to be accessed externally via the pin interface and internally via a registered host interface.

21.4.1

SIGNAL DESCRIPTION

This block doesn’t have any external signals that may be routed to the pin interface. This DMA Controller is intended to

be used internally to transfer large amounts of data without the embedded controller being actively involved in the trans-

fer.

21.4.2

HOST INTERFACE

The registers defined for the Internal DMA Controller are accessible by the various hosts as indicated in Section 21.9,

"EC-Only Registers".

21.4.3

DMA INTERFACE

Each DMA Master Device that may engage in a DMA transfer must have a compliant DMA interface. The following table

lists the DMA Devices in the MEC1322.

Note 21-1

The Device Number is programmed into field HARDWARE_FLOW_CONTROL_DEVICE of the DMA

Channel N Control register.

FIGURE 21-1:

INTERNAL DMA CONTROLLER I/O DIAGRAM

TABLE 21-2:

DMA CONTROLLER DEVICE SELECTION

Device Name

Device Number

(

Note 21-1)

Controller Source

SMBus 0 Controller

Slave

1Master

SMBus 1 Controller

Slave

3Master

SMBus 2 Controller

Slave

5Master

SMBus 3 Controller

Slave

7Master

SPI 0 Controller

Transmit

9Receive

SPI 1 Controller

Transmit

Receive

Internal DMA Controller

Power, Clocks and Reset

Interrupts

DMA Interface

Host Interface

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