MEC1322 datasheet(163/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 163

MEC1322

12.7.1

POWER DOMAINS

12.7.2

CLOCK INPUTS

12.7.3

RESETS

12.8

Interrupts

12.9

Low Power Modes

The Mailbox automatically enters a low power mode whenever it is not actively.

TABLE 12-2:

POWER SOURCES

Name

Description

VCC1

The logic and registers implemented in this block are powered by this

power well.

TABLE 12-3:

CLOCK INPUTS

Name

Description

48 MHz Ring Oscillator

This is the clock source for Mailbox logic.

TABLE 12-4:

RESET SIGNALS

Name

Description

VCC1_RESET

This signal resets all the registers and logic in this block to their default

state.

PWRGD

This signal is asserted when the main power rail is asserted. The Host

Access Port is reset when this signal is de-asserted.

TABLE 12-5:

SYSTEM INTERRUPTS

Source

Description

MBX_Host_SIRQ

This interrupt source for the SIRQ logic is generated when the EC_WR bit

is ‘1’ and enabled by the EC_WR_EN bit.

MBX_Host_SMI

This interrupt source for the SIRQ logic is generated when any of the

EC_SWI bits are asserted and the corresponding EC_SWI_EN bit are

asserted as well. This event is also asserted if the EC_WR/EC_WR_EN

event occurs as well.

This bit is also routed to the nSMI pin.

TABLE 12-6:

EC INTERRUPTS

Source

Description

MBX

Interrupt generated by the host writing the HOST-to-EC Mailbox register.

MBX_DATA

Interrupt generated by the host writing the MBX_DATA register.

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