PEB2256HT datasheet(67/490 Pages) INFINEON

67 / 490 page

FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

•Slave mode

In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route

clock. In case of LOS the DCO-R switches automatically to Master mode. If bit

CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.

• Master mode

In master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no clock

is supplied on pin SYNC. If an external clock on the SYNC input is applied, the DCO-R

synchronizes to this input. The external frequency can be 2.048 MHz (IPC.SSYF = 0)

or 8.0 kHz (IPC.SSYF = 1).

The following table shows the clock modes with the corresponding synchronization

sources.

The jitter attenuator meets the jitter transfer requirements of the ITU-T I.431 and G.735

to 739 (refer to Figure 17)

Table 13

System Clocking (E1)

Mode

Internal

LOS Active

SYNC

Input

System Clocks generated by DCO-R

Master

independent Fixed to

DCO-R centered, if CMR2.DCF = 0.

(CMR2.DCF should not be set)

Master

independent 2.048

MHz

Synchronized to SYNC input (external 2.048

MHz, IPC.SSYF = 0)

Master

independent 8.0 kHz

Synchronized to SYNC input (external 8.0 kHz,

IPC.SSYF = 1, CMR2.DCF = 0)

Slave

Fixed to

Synchronized to line RCLK

Slave

2.048

MHz

Synchronized to line RCLK

Slave

yes

Fixed to

CMR1.DCS = 0:

DCO-R is centered, if CMR2.DCF = 0.

(CMR2.DCF should not be set)

CMR1.DCS = 1:

Synchronized on line RCLK

Slave

yes

2.048

MHz

CMR1.DCS = 0:

Synchronized to SYNC input

(external 2.048 MHz)

CMR1.DCS = 1:

Synchronized on line clock RCLK

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