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PEB2256HT 데이터시트(PDF) 83 Page - Infineon Technologies AG

부품명 PEB2256HT
상세설명  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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제조업체  INFINEON [Infineon Technologies AG]
홈페이지  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description E1
Data Sheet
83
2002-08-27
4.2.3
CRC-Multiframe (E1)
The multiframe structure shown in Table 18 is enabled by setting bit: FMR2.RFS1/0 for
the receiver and FMR1.XFS for the transmitter.
Multiframe
:
2 submultiframes = 2
× 8 frames
Frame alignment
:
refer to section Doubleframe Format
Multiframe alignment :
bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern "001011"
CRC bits
:
bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14
CRC block size
:
2048 bit (length of a submultiframe)
CRC procedure
:
CRC4, according to ITU-T G.704 and G.706
E:
Spare bits for international use. Access to received information through bits
RSP.RS13 and RSP.RS15. Transmission is enabled by bits XSP.XS13 and
XSP.XS15. Additionally, automatic transmission for submultiframe error
indication is selectable.
S
a:
Spare bits for national use. Additionally, S
a-bit access through registers
RSA4…8 and XSA4…8 is provided. HDLC-signaling in bits S
a4 to Sa8 is
selectable.
C
1 …C4:
Cyclic redundancy check bits.
A:
Remote alarm indication. Additionally, automatic transmission of the A-bit is
selectable.
Table 18
CRC-Multiframe Structure (E1)
Sub-
Multiframe
Frame
Number
Bits 1 to 8 of the Frame
1
2
34
56
78
Multiframe
I
0
1
2
3
4
5
6
7
C
1
0
C
2
0
C
3
1
C
4
0
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
1
S
a4
1
S
a4
1
S
a4
1
S
a4
1
S
a5
1
S
a5
1
S
a5
1
S
a5
0
S
a61
0
S
a62
0
S
a63
0
S
a64
1
S
a7
1
S
a7
1
S
a7
1
S
a7
1
S
a8
1
S
a8
1
S
a8
1
S
a8
II
8
9
10
11
12
13
14
15
C
1
1
C
2
1
C
3
E*
C
4
E*
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
1
S
a4
1
S
a4
1
S
a4
1
S
a4
1
S
a5
1
S
a5
1
S
a5
1
S
a5
0
S
a61
0
S
a62
0
S
a63
0
S
a64
1
S
a7
1
S
a7
1
S
a7
1
S
a7
1
S
a8
1
S
a8
1
S
a8
1
S
a8



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